dusk os fork
git clone git://git.alexwennerberg.com/duskos
Log | Files | Refs | README | LICENSE

arm.txt (4752B) - raw

      1 # ARM assembler
      3 ARM instructions all encode to a 32-bit number and the way these encodings work
      4 incite us to deviate a little bit from the general Dusk assembler mechanism:
      5 Instead of pushing arguments to PS and then call the "operation writer" word, we
      6 begin the operation mnemonic and "accumulate" arguments into it.  When all
      7 arguments are accumulated, the number on PS is exactly what we want to write,
      8 which we can do with "le,", of which ",)" is an alias.
     10 For example, to write a "add" instruction with r4 as a destination (Rd), r5 as
     11 the first operand (Rn) and 42 as an immediate, we would do:
     13     add) r4 rd) r5 rn) 42 imm) ,)
     15 Symbol-wise, ")" means "accumulate", where the final ",)" means "write what has
     16 been accumulated".
     18 WARNING: this assembler will not prevent you from assembling nonsensical
     19 instructions, checks are minimal (it does check immediate ranges though). For
     20 example, this means that using "rn)" on "mov)" or "rd)" on "cmp)" results in a
     21 broken instruction.
     23 ## Generic words
     25 All operations work on registers and they pretty much all have a destination
     26 register and one or two operand registers. Each register has a constant word:
     28     r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15
     29     rFP rIP rSP rLR rPC
     31 These constants are meant to be used in conjunction with these accumulator
     32 words:
     34     rd) Destination register
     35     rn) First operand register
     36     rm) Second operand register
     37     rs) Used only for Multiply
     38     rdn) Shortcut for rd) rn) when they're the same
     40 Whenever there's a second operand register, the barrel shifter can be configured
     41 with these words which all have the ( op n -- op ) signature, "op" being the
     42 accumulated operation:
     44     lsl) lsr) asr) ror)     n = shift by "n" bits
     45     rlsl) rlsr) rasr) rror) n = register id containing the amount to shift by
     47 Immediates replace the rm) operand and can be specified with the imm) word.
     48 Shift encoding is automatically performed by imm) and will abort with an error
     49 message if the specified immediate can't be encoded.
     51 All operations can be conditionally executed. This condition is activated by one
     52 of these words:
     54     eq) ne) cs) cc) z) nz) hs) lo) mi) pl) vs) vc) hi) ls) ge) lt) gt) le) al)
     56 ## Data processing instructions
     58 All those instructions except mov) and mvn) have 3 operators:
     60     and) eor) sub) rsb) add) adc) sbc) rsc)
     61     tst) teq) cmp) cmn) orr) mov) bic) mvn)
     63 rn) shouldn't be used with mov) and mvn)
     65 To have the operation set the CPSR flags, you can use the word f) which sets the
     66 "S" bit of the instruction.
     68 tst) teq) cmp) and cmn) have an implied "f)".
     70 ## Multiply
     72 The multiply instruction, mul), has a different structure than other data
     73 processing instructions and does Rd := Rm * Rs. For this instruction, rn) can't
     74 be used and there's a rs) parameter word just for this instruction (Rs is
     75 generally set with the lsl), lsr), etc. family of words).
     77 Additionally, there's the possibility of making a Multiply+Add through the acc)
     78 word, which takes a register ID in parameter.
     80 Rd cannot be the same as Rm and rPC can't be used.
     82 The f) flag works with mul). Example usages:
     84     mul) r0 rd) r1 rm) r2 rs) ,)
     85     mul) r0 rd) r1 rm) r2 rs) r3 acc) ,)
     86     mul) r0 rd) r1 rm) r2 rs) f) ,)
     88 ## Single Data Transfer
     90 The str) and ldr) operations only use rd) and rn), with rd) being the register
     91 containing the value to store or the register being the target for the load
     92 operation. rn) is the register containing the target adress for the store/load
     93 operation.
     95 Many options come with those two operations and they are enabled with those
     96 words:
     98     +i)   op n -- op  Add offset "n" to rn)
     99     -i)   op n -- op  Subtract offset "n" from rn)
    100     +r)   op r -- op  Add offset in register "r" to rn)
    101     -r)   op r -- op  Subtract offset in register "r" from rn)
    102     pre)  op -- op    Add offset before transfer (default)
    103     post) op -- op    Add offset after transfer
    104     8b)   op -- op    Load/Store operation is 8-bit
    105     !)    op -- op    Write effective address back to rn)
    107 ## Swap
    109 The swp) instruction has the same base semantics as ldr) and str), that is, that
    110 rn) is the base address, but it doesn't support any kind of indexing. Only the
    111 8b) flag can be used.
    113     swp) r1 rd) r2 rn) r1 rm) ,) \ Swaps the value at address r2 with r1
    114     swp) r1 rd) r2 rn) r3 rm) ,) \ r3 --> [r2] --> r1
    116 ## Branching
    118 The b) bl) and bx) branching words differ from other mnemonic words because they
    119 need an argument from PS. In the case of b) and bl), it's a relative offset that
    120 follows rules described in doc/asm/intro, that is, that "0" must mean an
    121 infinite loop.
    123 In the case of bx), the argument is a register ID. Examples:
    125     begin abs>rel b) ,) \ infinite loop
    126     r0 bx) eq) ,) \ jump to address in R0 if Z is set